1. Field of the Invention
The present invention relates to a structure of a capacitor, and more particularly, it relates to a structure of a MIM (Metal Insulator Metal) type capacitor formed in a multilayer wiring structure of a semiconductor integrated circuit.
2. Description of the Background Art
An analog device is composed of resists, coils, condensers and so on, and a logic device is composed of MOS transistors and so on. In recent years, a formation of both the analog device and the CMOS logic device in a same chip, that is, a realization of one-chipped analog logic device is studied.
Conventionally, in a semiconductor device which the analog logic device is to be one-chipped, another photo mask has to be added to form a MIM capacitor. For example, 2 pieces in amount of the photo mask have to be added, one is for a processing of a lower electrode of the capacitor and another is for a processing of an upper electrode of the capacitor.
Besides, techniques in regard to the semiconductor device including the capacitor are described in Japanese Patent Application Laid-Open No. 2001-167974, Japanese Patent Application Laid-Open No. 2001-237375 and Japanese Patent Application Laid-Open No. 2000-228497.
However, according to such a conventional method of manufacturing the capacitor, a problem arises that a manufacturing cost increases which is caused by multiplication of the number of photo masks to be needed and of manufacturing processes.